synopsys lpddr45 controller
synopsys lpddr45 phy
DFI 5.0

配置流程

Step	Application	SVTB Task	Notes
1	Follow the PHYs power up procedure		See PUB databook for details
2	Program the DWC_ddrctl registers		Note 1
3	Disable auto-refreshes, self-refresh, powerdown and assertion of dfi_dram_clk_disable by setting: RFSHCTL0.dis_auto_refresh = 1, PWRCTL.powerdown_en = 0, PWRCTL.selfref_en = 0, PWRTL.en_dfi_dram_clk_disable = 0	reset_dut
4	De-assert reset signal core_ddrc_rstn
5	Set DFIMISC.dfi_init_complete_en to ‘0’ Set DFIMISC.dfi_reset_n to ‘1’	phy_init
6	Start PHY initialization and training by accessing relevant PUB registers	phy_init	See PUB databook for details
7	Poll the PUB register APBONLY.UctShadowRegs[0] = 1’b0	phy_init	See PUB databook for details
8	Read the PUB Register APBONLY.UctWriteOnlyShadow for training status	phy_init	See PUB databook for details
9	Write the PUB Register APBONLY.DctWriteProt = 0	phy_init	See PUB databook for details
10	Poll the PUB register APBONLY.UctShadowRegs[0] = 1’b1	phy_init	See PUB databook for details
11	Write the PUB Register APBONLY.DctWriteProt = 1	phy_init	See PUB databook for details
12	Poll the PUB register MASTER.CalBusy = 0	phy_init	See PUB databook for details
13	Set DFIMISC.dfi_init_start to ‘1’	phy_init
14	Poll DFISTAT.dfi_init_complete = 1	phy_init
15	Set DFIMISC.dfi_init_start to ‘0’	phy_init
16	The following registers may need to be updated after training has completed: ▪ RANKTMG0.diff_rank_wr_gap ▪ RANKTMG0.diff_rank_rd_gap ▪ DRAMSET1TMG2.rd2wr ▪ DRAMSET1TMG2.wr2rd ▪ DRAMSET1TMG24.rd2wr_s ▪ DRAMSET1TMG9.wr2rd_s ▪ DFITMG0.dfi_t_ctrl_delay ▪ DFITMG1.dfi_t_wrdata_delay ▪ DFITMG2.dfi_twck_delay (LPDDR5 only)	phy_init	Refer to relevant PHY documentation
17	Set DFIMISC.dfi_init_complete_en to ‘1’	phy_init
18	Set PWRCTL.selfref_sw to ‘0’	phy_init
19	Wait for DWC_ddrctl to move to normal operating mode by monitoring STAT.operating_mode signal	reset_dut
20	Set back registers in step 3 to the original values if desired

flowchart TD

    S1["Step 1: Follow PHYs power-up procedure"]
    S2["Step 2: Program DWC_ddrctl registers"]
    S3["Step 3: Disable auto-refresh, self-refresh, powerdown <br>and dfi_dram_clk_disable"]
    S4["Step 4: De-assert core_ddrc_rstn"]
    S5["Step 5: Set dfi_init_complete_en=0 and dfi_reset_n=1"]
    S6["Step 6: Start PHY init & training (access PUB registers)"]
    S7["Step 7: Poll PUB APBONLY.UctShadowRegs[0] = 0"]
    S8["Step 8: Read PUB UctWriteOnlyShadow (training status)"]
    S9["Step 9: Write PUB DctWriteProt = 0"]
    S10["Step 10: Poll PUB UctShadowRegs[0] = 1"]

    S11["Step 11: Write PUB DctWriteProt = 1"]
    S12["Step 12: Poll MASTER.CalBusy = 0"]
    S13["Step 13: Set dfi_init_start = 1"]
    S14["Step 14: Poll dfi_init_complete = 1"]
    S15["Step 15: Set dfi_init_start = 0"]

    S16["Step 16: Update training-dependent registers"]

    S17["Step 17: Set dfi_init_complete_en = 1"]
    S18["Step 18: Set selfref_sw = 0"]
    S19["Step 19: Wait for operating_mode to NORMAL"]
    S20["Step 20: Restore Step 3 registers if desired"]

    %% Flow connections
    S1 --> S2 --> S3 --> S4 --> S5 --> S6 --> S7 --> S8 --> S9 --> S10
    S10 --> S11 --> S12 --> S13 --> S14 --> S15 --> S16 --> S17 --> S18 --> S19 --> S20